As a cell size is small, cell array capacity is increased, and operation voltage is low, the possibility of fail in the cell is increased. The cell defect is caused by physical damage, impurity migration, write fatigue, and electrical signal fluctuation, and the like. A need exists for an Error Checking and Correcting (ECC) circuit in order to relieve such defects.
In a conventional cell array structure, there has been consumed many spaces for constructing the circuit. Therefore, it is difficult to effectively construct the ECC circuit in the conventional cell array structure. Consequently, there has been demanded a development of a new cell array structure capable of effectively constructing the ECC circuit.